- acer aspire 4755g
Processor / Chipset
- CPUIntel Core i5 2 i5-2410M / 2.3 GHz
- Max Turbo Speed2.9 GHz
- Number of CoresDual-Core
- CacheL3 cache - 3.0 MB
- 64-bit ComputingYes
- ChipsetMobile Intel HM65 Express
- FeaturesIntel Turbo Boost Technology 2.0,
Hyper-Threading Technology
Intel Core i5 680 and Core i7 870s CPUs in the pipeline
umors have it that Intel is planning on extending its Core i5 and Core i7 CPU lines. According toDigitimes, two new CPUs are on the way. The Core i5 680, 3.6GHz dual core part, 256KB of L2 cache per core and 4MB of L3 cache. The CPU is based on Intel's 32nm Clarkdale architecture and features a built-in 45nm integrated graphics processor. This chip will become Intel's fastest dual-core part and is expected to be priced (for a tray of 1,000) at $284. Then there's the Core i7 870s, which is like the i7 860 only clocked at a lower speed of 2.67GHz. This speed drop lowers the chips TDP from 95W to 82W. The price per thousand parts is expected to be $560.These CPUs, along with those from AMD, mean that there are some interesting times ahead of us
umors have it that Intel is planning on extending its Core i5 and Core i7 CPU lines. According toDigitimes, two new CPUs are on the way. The Core i5 680, 3.6GHz dual core part, 256KB of L2 cache per core and 4MB of L3 cache. The CPU is based on Intel's 32nm Clarkdale architecture and features a built-in 45nm integrated graphics processor. This chip will become Intel's fastest dual-core part and is expected to be priced (for a tray of 1,000) at $284. Then there's the Core i7 870s, which is like the i7 860 only clocked at a lower speed of 2.67GHz. This speed drop lowers the chips TDP from 95W to 82W. The price per thousand parts is expected to be $560.These CPUs, along with those from AMD, mean that there are some interesting times ahead of us
ปัญหาที่เป็นอุปสรรคของ PIPELINE (PIPELINE HAZARD)
เป็นผลกระทบจากการทำไปป์ไลน์เมื่อเกิดเหตุการณ์ที่ทำให้เกิดผลกระทบกับผลลัพธ์ของระบบ ยกตัวอย่างเช่น เมื่อคำสั่งบางคำสั่งจะมีการเขียนผลลัพธ์ลงบนตัวโอเปอร์แรนด์บางตัวที่ต้องถูกอ่านค่าจากอีกคำสั่งหนึ่ง หรือคำสั่งประเภท BRANCH ที่มีการกระโดดไปทำงานที่ส่วนอื่นก่อนแล้วจึงกลับมาทำคำสั่งต่อไปได้ ทำให้คำสั่งต่อไปไม่สามารถทำงานขนานกันไปได้ มี 3 ประเภทได้แก่
1.STRUCTURE HAZARDS : เกิดจากการขัดแย้งเมื่อ HARDWARE ไม่สามารถรองรับการรวมชุดคำ สั่งพร้อมกันในเวลาเดียวกัน เกิดการทับซ้อนกันเมื่อมีการ EXECUTE
2. DATA HAZARDS : เกิดจากการทีชุดคำ สั่งทับซ้อนกัน ไม่สามารถที่จะ EXECUTE
3.CONTROL HAZARD : PIPE LINE ที่แยกชุดคำสั่งไม่สามารถควบคุมสัญญาณได้
http://www.cnet.com/laptops/acer-aspire-4755g-6457/4507-3121_7-35268223.html
http://ark.intel.com/th/products/52224/Intel-Core-i5-2410M-Processor-3M-Cache-up-to-2_90-GHz
http://www.zdnet.com/blog/hardware/intel-core-i5-680-and-core-i7-870s-cpus-in-the-pipeline/7748
http://ark.intel.com/th/products/52224/Intel-Core-i5-2410M-Processor-3M-Cache-up-to-2_90-GHz
http://www.zdnet.com/blog/hardware/intel-core-i5-680-and-core-i7-870s-cpus-in-the-pipeline/7748
- Samsung Galaxy Mini
Architecture ARMv6Chipset Qualcomm MSM7227 CPU 600 MHz ARMv6 GPU Adreno 200
Bit width 32 Cores designed by ARM Holdings ARM11ARM11 Implements ARMv6 ISA
Arm Ltd. has pulled out all of the stops with its new ARM11 micro-architecture, which implements the new ARM6 instruction set. Whether it's SIMD multimedia acceleration, floating point, compact Thumb16 instructions, or even Java, the new micro-architecture does everything. Delivered as IP, ARM11 can include such options as the vector floating-point coprocessor. ARM11 uses a new eight-stage pipeline that supports out-of-order execution. Initial top speed is 750 MHz via a 1.3-µm process. Next-generation 1.0-µm versions should hit 1-GHz speeds.This micro-architecture continues the ARM family's use of the AMBA bus and retains the low-power operation that ARM is known for. Power consumption is under 0.4 mW/MHz, including cache controllers. Combined with the multimedia instructions, it makes an excellent choice for portable, wireless multimedia devices. The ARM11 memory subsystem improves task switching. It also reduces bus accesses, thereby lowering power requirements.New load/store exclusive instructions allow more efficient semaphore implementation, making ARM11 well suited for multiprocessor environments. Enhanced exception handling is provided via new vectored interrupt support.The ARM11 architecture tolerates unaligned data. In addition, a status bit controls big-endian and little-endian operation, enabling the processor to work well with non-ARM processors and DSPs. Overall, the ARM11 offers a significant architectural advance.ARM Processor Architecture
ARM architecture forms the basis for every ARM processor. Over time, the ARM architecture has evolved to include architectural features to meet the growing demand for new functionality, high performance and the needs of new and emerging markets. There are currently two ARMv8 profiles, the ARMv8-A architecture profile for high performance markets such as mobile and enterpise, and the ARMv8-R architecture profile for embedded applications in automotive and industrial control.
The ARM architecture supports implementations across a wide range of performance points, establishing it as the leading architecture in many market segments. The ARM architecture supports a very broad range of performance points leading to very small implementations of ARM processors, and very efficient implementations of advanced designs using state of the art micro-architecture techniques. Implementation size, performance, and low power consumption are key attributes of the ARM architecture.ARM developed architecture extensions to provide support for Java acceleration (Jazelle®), security (TrustZone®), SIMD, and Advanced SIMD (NEON™) technologies. The ARMv8-architecture adds a Cryptographic extension as an optional feature.The ARM architecture is similar to a Reduced Instruction Set Computer (RISC) architecture, as it incorporates these typicalRISC architecture features:- A uniform register file load/store architecture, where data processing operates only on register contents, not directly on memory contents.
- Simple addressing modes, with all load/store addresses determined from register contents and instruction fields only.
Enhancements to a basic RISC architecture enable ARM processors to achieve a good balance of high performance, small code size, low power consumption and small silicon area.
Reference
http://en.wikipedia.org/wiki/Samsung_Galaxy_Mini
http://en.wikipedia.org/wiki/ARM_architecture#ARM_cores
http://www.gsmarena.com/samsung_galaxy_mini_s5570-3725.php
http://www.arm.com/products/processors/instruction-set-architectures/index.php
http://electronicdesign.com/dsps/hardware-directory-arm11-implements-armv6-isa
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